Testing techniques for VLSI circuits are undergoing many changes. The predominant method for testing digital circuits consists of applying a set of input stimuli to the IC and monitoring the logic levels at primary outputs. If, for one or more inputs, there is a discrepancy between the observed output and the expected output then the IC is declared to be defective.
A new approach to testing digital circuits is known as IDDQ testing. In IDDQ testing, the steady state supply current, rather than the logic levels is monitored at the primary outputs. Research suggests that IDDQ testing can significantly improve the quality and reliability of fabricated circuits.
IDDQ testing is a test technique based on measuring the quiescent supply current of the device under test. The decision criterion is based on the fact that a CMOS circuit does not draw any significant current when in a stable situation. In a quiescent state only the leakage current flows, which may typically be neglected. The fact that under certain conditions a significant current flows when the device under test is in a quiescent state indicates the presence of a manufacturing defect in the circuit. A defect capable of causing a current increase can directly influence the functionality of the circuit (functional failure) or otherwise negatively effect the lifetime and reliability of the circuit ((early) lifetime failure).
As devices continue to scale down into the deep sub-micron region, leakage current becomes more sensitive to the process. Usually, a big channel leakage current introduced by defects in the SRAM bit cell, for example, the pass transistor defect, may cause functionality and IDDQ failures in the SRAM. Among these two failures, IDDQ failure contributes to a large portion of SRAM yield loss, especially for chips used in the portable device which is sensitive to the leakage. In a conventional column redundancy scheme, only the functionality failure can be fixed by replacing the failed column with a good one. However, the IDDQ failure is still there because the leakage path exists in the failed column.
It is desirable to not only replace a failed column with a good column, but also to be able to eliminate the leakage contributing to, for example, an IDDQ failure.